In this paper, a novel packet switch architecture for mesh-connected multiprocessors based on the use of a set of input FIFO buffers and an output register matrix is proposed. Simple static routing is assumed, with each packet split into some independently routed m-bit-wide flits. In contrast to the-state-of-the-art VOQ-based switch architectures, the proposed architecture is shown to enable the processing of the incoming packet streams in a parallel pipelined fashion with no internal speedup required. Furthermore, the device achieves at least 78% throughput for uniformly distributed traffic, and an asymptotic higher bound of 100%.
Key words: Multiprocessor, Mesh topology, Packet switching, Input-queued switch, FIFO-buffer, Flit, Pipelining, Throughput.
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