Improved Testability Method For Mesh-Connected VLSI Multiprocessors
Jamil Al Azzeh.
Abstract
The problem of in-operation embedded hardware-level fault detection in mesh-connected VLSI multiprocessors is considered. A new approach to the multiprocessor test based on the mutual inter-unit checking is presented, which allows increasing the successful fault detection probability. Formal rules are defined for forming sets of testing and tested neighbors for each unit which are invariant to the location of the unit within the topological structure of the multiprocessor and its dimension. The final test result for each processor unit is formed by applying the majority operator to the individual faulty/healthy tags calculated by all testing neighbors. The formulae to determine the number of testing neighbors for each unit depending on the dimension of the multiprocessor are given. The successful fault detection probability is evaluated in the case when the proposed approach is used; the successful fault detection probability vs. multiprocessor dimension and the successful fault detection probability vs. the individual test unit reliability dependencies are investigated. The proposed approach is shown to provide increased successful fault detection probability compared to the self-test for all practically significant cases.
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