As a new technique for reducing leakage power in deep sub-micron technology node, Sleepy-Pass Gate Keeper technique is proposed in this paper, which is a hybrid of Sleepy-Pass Gate and Sleepy Keeper techniques. Performance verifications were performed via LTspice simulations of 3-input NAND and 3-input NOR gates designed to implement the proposed technique. Performance comparisons with equivalent NOR3 and NAND3 gates based on Sleepy Keeper and Sleepy-Pass Gate techniques, revealed that the proposed technique outperforms the counterparts in terms of average leakage power consumption. Average leakage power of NAND3 and NOR3 gates using the new technique are 32% and 40% of those of Sleepy Keeper NAND3 and NOR3, and 57% and 20% of those of Sleepy-Pass Gate NAND3 and NOR3, respectively.
Key words: Leakage power, Propagation delay, Sub-threshold current, Power-delay-product.
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