Domino logic finds a wide variety of applications in both static and dynamic random-access memories and in high-speed microprocessors. However, the main limitation of the domino logic-circuit family is the trade-off between the noise immunity and speed. In order to resolve such a trade-off, this paper proposes a domino logic that is based on floating-gate MOS (FGMOS) transistors. Compact-form expressions are derived for the noise margins for the low and high inputs as well as the propagation delays. The proposed scheme is verified by simulation adopting the 45 nm CMOS predictive technology model (PTM) with a power-supply voltage of 1 V. The obtained results unveil that the proposed domino logic outperforms the conventional domino logic in terms of the power-delay product and the energy-delay product when realizing wide fan-in OR gates. The realized, with the proposed scheme, 16-input OR gate has an average power consumption of 3.7 µW and a propagation delay of 51 ps.
Key words: Domino logic; Floating-gate MOS transistor; Noise margin; Time delay.
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